Improved Switching Characteristics of Fast Power MOSFETs Applying Solder Bump Technology

The impact of a reduced package stray inductance on the switching performance of fast power MOSFETs is discussed applying advanced 3D packaging technologies. Starting from an overview over new packaging approaches, a solder bump technology using a flexible PI substrate is exemplarily chosen for the evaluation. Measurement techniques to determine the stray inductance are discussed and compared with a numerical solution based on the PEEC method. Experimental results show the improvement of the voltage utilization while there is only a slight impact on total switching losses.

Introduction
Fast power MOSFETs in the voltage class up to 100V realize very high current and power densities while at the same time switching transients achieve times below 50 nanoseconds. Due to the fast switching, parasitic inductances in the circuit have significant impact on converter power since overvoltages and oscillations reduce the voltage margin and hence, the maximum power rating. Optimizing the packaging of the devices is an important step to improve the utilization of the semiconductors and make use of their full current and voltage ratings.Usually, state-of-the-art devices are assembled in discrete housing, or in power modules.

The semiconductor dice are soldered to a leadframe or DBC, and thick wire bond technology is applied to contact the top source and gate pads of the dice as well as the external terminals. The wire bonds are a bottleneck with regard to stray inductance and the ohmic losses, that is, the current utilization of the chips.Further drawbacks include reliability issues and limitations with regard to 3D integration.
Several new packaging technologies have been proposed to overcome the structural limits of the wire bond technology and the related reliability problems as well as the reliability and thermal constraints associated with the die solder contact. Only a few ideas have made the transition to market yet, for example, the discrete International Rectifier “DirectFET”. The (“low-temperature joining technique”) LTJT, which is a promising alternative for the die solder bond, is close to realization for automotive applications.

Apart from the LTJT, most of the proposed packaging solutions concentrate on a substitution of the wire bonds including alternatives like ribbon bonding or spring contacts as well as planar interconnect technologies in 3-dimensional stacked assemblies. The latter include solutions with a prestructured circuit board, for example, a copper frame, a flexible substrate, or a second DBC that is usually soldered to the top side of the dice by solder bumping.Examples are the “flip-chip-on-flex” technology and the “power ball grid array” technology applying two DBCs. In derivatives of these solutions, copper posts or cylinders are soldered between the two substrates, which might be necessary for high-voltage applications. Other feasible alternatives cover solutions where the electrical circuit layout is structured during a planar integration process with metallurgically-formed interconnects leading to a multilayer assembly. Typical examples are the planar integration with an “embedded power stage” or the “Planar Power Polymer Packaging Technology” . Table 1 summarizes the basic material and geometrical data of the described 3D approaches.

There are several advantages anticipated from 3D sandwich assemblies including higher power density due to a compact layout, reduced interconnect resistances, and higher current rating compared to wire bonds as well as less parasitic stray inductance giving improved switching behavior and reduced overvoltage. Furthermore, improved heat paths and the possibility to apply double-side cooling concepts due to a second planar surface are expected. The compact integration of control electronic components into the power assembly might be a further benefit.

The reliability of 3D assemblies, on the other hand, has to be investigated thoroughly. Difficulties are to be expected, since several materials with different CTEs (coefficient of thermal expansion) are joined with large contact areas. The focus of this paper is the evaluation of the switching behavior of fast MOSFETs applying sandwich-type packaging. Exemplarily, a solder bump technology is used with the top contacts of the dice soldered to a flexible PI substrate. The analysis is based on experimental results of a half-bridge topology in buck converter configuration. The prototypes are built with 100 V-MOSFETs (Infineon OptiMOS, chip area 26mm2) with high current rating and low on-state resistance in the range below 5mΩ, and Schottky diodes (IXYS DWS 36-80 A). The wire bonds are limiting the chip utilization for this kind of MOSFET due to their current rating given by the maximum wire temperature.

SUMMARY
In this paper, the impact of a reduced package stray inductance on the switching performance of fast power MOSFETs is discussed applying advanced 3D packaging technologies. Starting from an overview over new packaging technologies, a solder bump technology using a flexible PI substrate is exemplarily chosen for the evaluation. Measurement techniques to determine the stray inductance of the package are discussed, showing that accurate results may be achieved applying an externally switched current approach while double-pulse measurements and the use of an impedance analyzer are not feasible for the package characterization.

Good agreement with a numerical solution based on the PEEC method is found. The relevance of a low stray inductance for fast switching MOSFETs is obvious from the measurement of the voltage overshoot allowing operating the new device at significantly higher DC voltages—up to 25%—than standard packages. The impact on the switching losses, however, was found to be less pronounced due to the reduced losses at turnon.

As an additional benefit, also the package resistance is reduced compared to standard housing while at the same time larger copper areas substituting the wire bonds are able to carry higher amounts of current. This thermal aspect is discussed further in [13]S. Dieckerhoff, T. Wernicke, T. Kirfe, et al., “Electric characteristics of planar interconnect technologies for power MOSFETs,” in Proceedings of the IEEE Power Electronics Specialists Conference (PESC ’07), pp. 1036–1042, Orlando, Fla, USA, June 2007.

by : Sibylle Dieckerhoff, ThiesWernicke, Christine Kallmayer, Stephan Guttowski, and Herbert Reichl

Source : DOWNLOAD